1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device containing a field effect transistor equipped with a protective diode.
2. Description of the Related Art
On the semiconductor devices of this kind, there has been proposed a semiconductor device including a vertical-type field effect transistor equipped with a protective Zener diode formed commonly in a semiconductor substrate, as disclosed in Japanese Patent Laid-Open No. 98557/1984. FIG. 1 is a sectional view of this conventional semiconductor device. In this vertical-type field effect transistor, a drain electrode 9" is formed on the lower surface of a semiconductor substrate 4" consisting of an N.sup.+ -type layer 21" and an N-type drain region 22" formed on this N.sup.+ -type substrate 21". In the N-type drain region 22", a plurality of P-type base regions 3" are formed with a predetermined space between them by diffusion from the upper surface of the semiconductor substrate 4". In each P-type base region 3", an N.sup.+ -type source regions 10" are formed by impurity diffusion from the surface side, and a P.sup.+ -type base contact diffused region 11" is formed in the N.sup.+ -source region 10". On a surface portion 22a" of the N-type drain region 22" between the P-type base regions 3" and on the surfaces of the P-type base region 3" and the source region 10", a gate polysilicon electrode 5" is formed with a gate oxide film 6" interlaid between them. A source electrode 8" is formed on the substrate 4" to contact with both the source region 10" and the P.sup.+ -base contact diffused region 11", while an interlayer insulation film 12" is formed between this source electrode 8" and the gate electrode 5". In this way, the vertical-type field effect transistor having the source electrode 8", the N.sup.+ -source region 10", the P-type base region 3", the N-type drain region 22", the N.sup.+ -type drain region 21" and the drain electrode 9" is formed.
Furthermore, the bottom part of the P-type base region 3" is so formed as to contact with the N.sup.+ -drain layer 21", to form a Zener diode at the bottom part of each base region 3". Therefore, the Zener diode having a lower breakdown voltage than that determined by the drain region 22" and the base region 3" is formed between the source and the drain, and a breakdown resistance between the source and the drain of the vertical-type field effect transistor is increased. Additionally, numeral 14" denotes a field thermal oxide film.
An equivalent circuit of the semiconductor device of this prior art has a construction wherein a Zener diode D.sub.Z for protection is connected between the drain D and the source S of FET 30 as shown in FIG. 2.
Although the above-described prior art may be realized with relative ease in the vertical-type field effect transistor, it is hard to apply this device structure to a horizontal-type field effect transistor. Moreover, in order to alter the voltage of the Zener diode in the prior art, it is necessary to alter the impurity concentration of the P-type base region 3". However, since the channel region of the prior-art field effect transistor is formed on the surface of this P-type base region 3", a threshold voltage V.sub.T of the field effect transistor is also altered when the impurity concentration of this base region 3" is altered. Therefore, it has been difficult to alter the voltage of the Zener diode without changing the threshold voltage V.sub.T according to the prior art.
As for the horizontal-type field effect transistor, it is conceivable to form a Zener diode in a semiconductor substrate separately from the horizontal-type field effect transistor and connect them as shown in FIG. 3.
In this structure, N-type wells 52" and 56" are provided in a P-type semiconductor substrate 51". A P-type base 53", an N-type high impurity concentration source 54" and an N-type high impurity concentration impurity regions 55" are formed in the surface portion of the well 52". A gate 58" is formed at least on a channel-forming region of the base 53" with a gate insulation film interlaid therebetween. A P-type high impurity concentration region 53a" and an N-type high impurity concentration region 55" are provided in the surface portion of the well 56". A source electrode 59s" is connected to the P-type high impurity concentration region 53a" in the well 56", the source 54" and base 53". A drain electrode 59d" is connected to a drain contact region 55" in the well 52" and the N-type high impurity concentration region 55" in the well 56". Herein the N-type well 56" and the P-type high impurity concentration regions 53a" constitute a Zener diode for protection, for which the former operates as a cathode and the latter as an anode.
Accordingly, an equivalent circuit of this semiconductor device also has a construction wherein a Zener diode D.sub.Z for protection is connected between the drain D and the source S of FET 30 as shown in FIG. 2.
Since the Zener diode for protection against a surge and the horizontal-type field effect transistor are formed separately on the same semiconductor substrate 51" in the semiconductor device described above, the area occupied by those diode and transistor is increased when the current capacity of the Zener diode is made large sufficiently. This obstructs the attainment of high density of the device, and makes the structure complicated to result in a fault of tending to cause an unstable operation, such as latch-up.